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@Vyor_1
source link: https://twitter.com/andreif7/status/1395869550667784194
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It doesn't crush it, it barely beats it in single thread only and that's at 5nm where CZN is on 7nm.
Multithread it gets absolutely crushed in perf per watt, because 8c/16t with high enough IPC and clocks will beat a 4 big core 4 little core ARM chip that has high IPC but-
really low clocks. And it isn't like the power draw is that different either, CZN-U is 15w, M1 is, what, 24w fully stressed, which includes the iGPU of course, but core only I can't imagine it's that much more or less power than a mere 15w.
That comparison is dumb, you can't do perf/w at ISO power and then normalise again for process power at N5, you need to do process performance which is +15% which doesn't close the gap. Achieving higher efficiency via high IPC is much harder.
Furthermore it's 31W not 3.8W. AMD power metrics don't contain L3 or anything else, the same figures on the M1 was the cluster, and package was just 1-2W above that. The real perf/W gap is gigantic.
If other cores were power gated (likely for any modern design), cluster pwr should be close to single core power.
Pkg vs pkg is not interesting bc Z3 IO is more flexible (replaceable RAM, more RAM, more connectivity). But good point about L3 pwr, anyone have figures?
There's no way to differentiate L3 power from package minus core power, there's no energy counters for that domain. We just know AMD has bad IOD power. Using the mobile parts for comparisons is the better route to take but while it's better than desktop it's still far away.
Yeah, APU pkg power should be lower. But AMD still has more flexible connectivity, which comes at a power cost. Pretty darn hard to compare the two platforms - they're built with very different goals in mind.
and one of them is tuned to the point a small voltage drop will crash the system; and it ain't the AMD chips.
What do you mean? Afaik there's no voltage tweaking (or adjustable anything) on M1
The irony is that we've actually had workloads consistently crash some Zen3 chips due to voltage drops at extreme transients and gave AMD a reproducible binary for it to debug. Put him on block and end the clownshow.
That's actually fascinating! Are those binaries public?
It was my MT bandwidth test so it's not public, affected our 5900X during the launch review. Think it crashed once it reached load on the L2 on all cores synchronously (from atomic busy wait & start loop), wasn't very real world but consistently required power cycle to recover.
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