Neoverse S3 enables Arm-based chiplets - Infrastructure Solutions blog - Arm Com...

Introducing the 3rd Generation of Neoverse System IP

The Neoverse S3 products introduce our 3rd generation of infrastructure-specific system IP, the ideal foundation for next generation infrastructure SOCs, for applications ranging from HPC and Machine learning down to Edge and DPU. The S3 chassis is focused on delivering key innovations like to Chiplets, Confidential Compute and industry standards like UCIe, DDR5, CXL 3.1 and PCIe Gen5/Gen6 off-the-shelf capabilities to our partners. Neoverse S3 provides the suite of system IP that offers new composability, increased IO throughput, and enhanced security. Key features of Neoverse S3 products include:

• Arm RME for Confidential Compute with device assignment and aligned with industry standard DPE for ‘in use’ data protection
• Upgraded IO and memory systems for PCIe Gen6, CXL 3.1, DDR5 and HBM3
• Standardized Chiplet interfaces with AMBA CHI C2C over UCIe with a defined chiplet development kit to pair with an Arm compute

Enabling Confidential Compute

Security is a system level problem touching all IP in an SoC. Encryption has been used for many years to securely store or transmit data. This is referred to as protecting data “at rest” or “in transit”. The latest hardware-based security advancement is to protect data while it is “in use” in memory. The industry term for encrypting data in memory is Confidential Computing. The Armv9 architecture supports Arm Confidential Computing Architecture using a hardware technique we call “Realm Management Extension” or RME. The Neoverse S3 products are the first to support RME, allowing Arm Neoverse V3 cores to support fully encrypted cloud VMs.

IO devices like PCIe and CXL attached peripherals (such as a NIC or Accelerator) are potential security threats. Neoverse S3 System IP ensures external attached devices only see the memory allowed without impacting application performance. This is done through a technique called “Device Assignment” that allows peripheral devices to DMA (directly transfer data to memory) into encrypted memory. In addition to the security benefit, this also allows attached devices to share data while bypassing heavy layers of software, greatly enhancing I/O performance.

This essential capability of connecting efficient general-purpose compute with highly performant workload accelerators is at the heart of Arm’s latest Neoverse Compute Subsystem (CSS) products, Neoverse CSS V3 and Neoverse CSS N3. CSS products are engineered to help Arm partners deliver workload-optimized custom silicon to market more quickly, more efficiently, and at lower cost than they could do so previously. The Microsoft Azure Cobalt 100 CPU is a result of this new hardware/software co-development model enabled by Neoverse CSS. These CSS products represent the future of Arm Neoverse-based solutions, as we work as an industry and as an ecosystem of the longer-term goal of enabling lower-cost, reusable Arm-based chiplets. And none of this is possible without the unsung hero Neoverse S3 system IP as the foundation.

Supporting Industry Standards and Chiplets

Industry standards like PCIe Gen5/Gen6, CXL 3.1, UCIe and DDR5 are key for every infrastructure class SoC. Unfortunately, it is not trivial to implement these standards right. With the Neoverse S3 generation, Arm does a lot of the heavy lifting to enable support of these standards, including interoperability testing with key third party IPs like controllers and PHYs. Neoverse makes these industry standards off-the-shelf capabilities for our partners, so they can focus on their differentiation and specialization.

Technology advances are becoming extremely expensive and not all aspects of design physics are scaling equally. This basically means only certain aspects of systems (eg: CPU’s) can meaningfully take advantage of technology advances. Chiplets enable breaking down a System on Chip (SoC) into System on a Package (SoaP) which enables using different technology nodes to be adopted economically to build the system. SoaP enables modularity to create solutions, amortizing the cost of chiplet development across different solutions.

This modularity, though, should not come at a cost of violating architectural or software complexity. Arm Neoverse solutions enable chiplets using standardized interfaces with predefined chiplet profiles. This enables the various chiplet vendors in the Arm Neoverse ecosystem to build their chiplets to be compatible with Neoverse CSS.  The chiplet standards include:

1. AMBA CHI C2C covers the application and link layer protocols for physical transport of the bits across the SoaP sysbsystems.
2. Arm Chiplet System Architecture covers the architectural compliance to define address translation, interrupt handling, system management, security aspects of
3. Arm Base System Architecture covers the needs for standard software

To further accelerate the adoption of AMBA CHI C2C and chiplets, Arm is providing a Chiplet design kit based on the Neoverse S3 chassis. This design kit provides the foundation for IO coherent and fully coherent acceleration or disaggregation chiplets.

A Foundation for Neoverse CSS and Custom Silicon

Figure 1. Arm Neoverse system diagram showing the Neoverse S3 chassis: CMN S3, MMU S3, and NOC S3

The Neoverse S3 generation is comprised of Neoverse CMN S3, Neoverse MMU S3 and Neoverse NOC S3, together they form a robust and proven platform for partners to build their SOCs around.

CMN S3 builds on the legacy of CMN-700 IP, forming the coherent freeways that keep ever more performant and data hungry Neoverse CPUs fed. CMN S3 is Confidential compute enabled and built for the new chiplet world, while improving performance and scalability, which is a key for interconnects.

CMN S3’s ability to connect CPU and accelerator chiplets securely and with high performance (high-bandwidth, low-latency) is essential for developing the power efficient, cost-effective, workload-optimized SoCs that power modern infrastructure. All leading cloud providers rely upon Data Processing Units (DPUs) to offload security, storage, and networking functions from host CPUs. They are also deploying and developing GPUs, NPUs, and TPUs to accelerate the AI and ML capabilities pervading modern cloud software. Meanwhile, telecommunications providers are deploying heterogeneous CPU+accelerator SoCs into 5G RAN and edge infrastructure.

MMU S3 builds on our industry standard MMU-700 IP, providing performant, Confidential compute aware and PCIeG6/CXL3.1 ready IO memory management unit for on-chip, chiplet and add-in card applications.

NOC S3 is our new Non-coherent interconnect built on NI-700, NOC S3 is purpose built for IO coherent acceleration chiplets, it enables partners to build disaggregated SOCs with same ease and performance that partners are used to with on-chip AMBA based designs.

The Neoverse S3 products are our 3rd generation of Neoverse System IP, and they form the foundation for our CSS V3 and CSS N3. This platform enables essential capability needed to build world class infrastructure SOCs ranging from Cloud serves to edge DPUs. This platform is compliant with key industry standards and is the industry standard. S3 will make confidential compute and chiplets off-the-shelf capabilities for our partners to incorporate into their next generation of innovative custom silicon.

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