Commits · amd-staging-drm-next · Alex Deucher / linux · GitLab - JOYK Joy of Geek, Geek News, Link all geek

Commits · amd-staging-drm-next · Alex Deucher

Dec 14, 2023

drm/amd/pm: fix a double-free in amdgpu_parse_extended_power_table

Zhipeng Lu authored 20 hours ago

The amdgpu_free_extended_power_table is called in every error-handling
paths of amdgpu_parse_extended_power_table. However, after the following
call chain of returning:

amdgpu_parse_extended_power_table
  |-> kv_dpm_init / si_dpm_init
      (the only two caller of amdgpu_parse_extended_power_table)
        |-> kv_dpm_sw_init / si_dpm_sw_init
            (the only caller of kv_dpm_init / si_dpm_init, accordingly)
              |-> kv_dpm_fini / si_dpm_fini
                  (goto dpm_failed in xx_dpm_sw_init)
                    |-> amdgpu_free_extended_power_table

As above, the amdgpu_free_extended_power_table is called twice in this
returning chain and thus a double-free is triggered. Similarily, the
last kfree in amdgpu_parse_extended_power_table also cause a double free
with amdgpu_free_extended_power_table in kv_dpm_fini.

Fixes: 84176663

 ("drm/amd/pm: create a new holder for those APIs used only by legacy ASICs(si/kv)")
Signed-off-by: 
Signed-off-by:

7176f46c

gpu/drm/radeon: fix two memleaks in radeon_vm_init

Zhipeng Lu authored 20 hours ago

When radeon_bo_create and radeon_vm_clear_bo fail, the vm->page_tables
allocated before need to be freed. However, neither radeon_vm_init
itself nor its caller have done such deallocation.

Fixes: 6d2f2944

 ("drm/radeon: use normal BOs for the page tables v4")
Signed-off-by: 
Signed-off-by:

4f532fb2

drivers/amd/pm: fix a use-after-free in kv_parse_power_table

Zhipeng Lu authored 21 hours ago

When ps allocated by kzalloc equals to NULL, kv_parse_power_table
frees adev->pm.dpm.ps that allocated before. However, after the control
flow goes through the following call chains:

kv_parse_power_table
  |-> kv_dpm_init
        |-> kv_dpm_sw_init
	      |-> kv_dpm_fini

The adev->pm.dpm.ps is used in the for loop of kv_dpm_fini after its
first free in kv_parse_power_table and causes a use-after-free bug.

Fixes: a2e73f56

 ("drm/amdgpu: Add support for CIK parts")
Signed-off-by: 
Signed-off-by:

a2bfd4ad

drm/amd/pm: fix a double-free in si_dpm_init

Zhipeng Lu authored 22 hours ago

When the allocation of
adev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries fails,
amdgpu_free_extended_power_table is called to free some fields of adev.
However, when the control flow returns to si_dpm_sw_init, it goes to
label dpm_failed and calls si_dpm_fini, which calls
amdgpu_free_extended_power_table again and free those fields again. Thus
a double-free is triggered.

Fixes: 841686df

 ("drm/amdgpu: add SI DPM support (v4)")
Signed-off-by: 
Signed-off-by:

bfbecc17

drm/amd/pm: Remove unneeded semicolon

Yang Li authored 1 day ago


./drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c:1418:2-3: Unneeded semicolon

Reported-by: 
Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=7743


Signed-off-by: 
Signed-off-by:

47b2e76d

drm/amdgpu/debugfs: fix error code when smc register accessors are NULL

Alex Deucher authored 2 weeks ago

Should be -EOPNOTSUPP.

Fixes: 5104fdf5

 ("drm/amdgpu: Fix a null pointer access when the smc_rreg pointer is NULL")
Reviewed-by: 
Signed-off-by:

20f0989e

drm/amd/display: Add 3x4 CTM support for plane CTM

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 23 hours ago


Create drm_color_ctm_3x4 to support 3x4-dimension plane CTM matrix and
convert DRM CTM to DC CSC float matrix.

v3:
- rename ctm2 to ctm_3x4 (Harry)

Reviewed-by: 
Signed-off-by:

2d4457c2

drm/amd/display: add plane CTM support

Melissa Wen authored 4 weeks ago


Map the plane CTM driver-specific property to DC plane, instead of DC
stream. The remaining steps to program DPP block are already implemented
on DC shared-code.

v3:
- fix comment about plane and CRTC CTMs priorities (Harry)

Reviewed-by: 
Signed-off-by:

8c805d0e

drm/amd/pm: add power save mode workload for smu 13.0.10

Kenneth Feng authored 2 days ago


add power save mode workload for smu 13.0.10, so that in compute mode,
pmfw will add 35mv voltage margin since some applications requres higher
voltages.

Signed-off-by: 
Reviewed-by:

26193b87

drm/amdgpu/vpe: enable vpe dpm

Peyton Lee authored 3 days ago
```
enable vpe dpm

Signed-off-by: 
Reviewed-by: 
```
c9412c9b

drm/amd/display: add plane CTM driver-specific property

Melissa Wen authored 4 weeks ago


Plane CTM for pre-blending color space conversion. Only enable
driver-specific plane CTM property on drivers that support both pre- and
post-blending gamut remap matrix, i.e., DCN3+ family. Otherwise it
conflits with DRM CRTC CTM property.

Reviewed-by: 
Signed-off-by:

7e61f69a

drm/amd/display: copy 3D LUT settings from crtc state to stream_update

Joshua Ashton authored 4 weeks ago


When commiting planes, we copy color mgmt resources to the stream state.
Do the same for shaper and 3D LUTs.

Reviewed-by: 
Signed-off-by: 
Co-developed-by: 
Signed-off-by:

c1f31e39

drm/amd/pm: support return vpe clock table

Peyton Lee authored 3 days ago


pm supports return vpe clock table and soc clock table

Signed-off-by: 
Reviewed-by:

21d59e48

drm/amdgpu: fix ftrace event amdgpu_bo_move always move on same heap

Wang, Beyond authored 3 days ago


Issue: during evict or validate happened on amdgpu_bo, the 'from' and
'to' is always same in ftrace event of amdgpu_bo_move

where calling the 'trace_amdgpu_bo_move', the comment says move_notify
is called before move happens, but actually it is called after move
happens, here the new_mem is same as bo->resource

Fix: move trace_amdgpu_bo_move from move_notify to amdgpu_bo_move

Signed-off-by: 
Reviewed-by:

c548df32

Dec 13, 2023

drm/amd/display: allow newer DC hardware to use degamma ROM for PQ/HLG

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 1 day ago


Need to funnel the color caps through to these functions so it can check
that the hardware is capable.

v2:
- remove redundant color caps assignment on plane degamma map (Harry)
- pass color caps to degamma params

v3:
- remove unused color_caps parameter from set_color_properties (Harry)

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

49e94535

drm/amd/display: add plane blend LUT and TF support

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 1 day ago


Map plane blend properties to DPP blend gamma. Plane blend is a
post-3D LUT curve that linearizes color space for blending. It may be
defined by a user-blob LUT and/or predefined transfer function. As
hardcoded curve (ROM) is not supported on blend gamma, we use AMD color
module to fill parameters when setting non-linear TF with empty LUT.

v2:
- rename DRM TFs to AMDGPU TFs

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

631acbc9

drm/amd/display: handle empty LUTs in __set_input_tf

Joshua Ashton authored 4 weeks ago


Unlike degamma, blend gamma doesn't support hardcoded curve
(predefined/ROM), but we can use AMD color module to fill blend gamma
parameters when we have non-linear plane gamma TF without plane gamma
LUT. The regular degamma path doesn't hit this.

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

75d10452

drm/amd/display: add plane 3D LUT support

Melissa Wen authored 4 weeks ago


Wire up DC 3D LUT to DM plane color management (pre-blending). On AMD
display HW, 3D LUT comes after a shaper curve and we always have to
program a shaper curve to delinearize or normalize the color space
before applying a 3D LUT (since we have a reduced number of LUT
entries).

In this version, the default values of 3D LUT for size and bit_depth are
17x17x17 and 12-bit, but we already provide here a more generic
mechanisms to program other supported values (9x9x9 size and 10-bit).

v2:
- started with plane 3D LUT instead of CRTC 3D LUT support

v4:
- lut3d_size is the max dimension size instead of # of entries

Reviewed-by: 
Signed-off-by:

3c6e4a6e

drm/amdgpu: warn when there are still mappings when a BO is destroyed v2

Christian König authored 1 week ago
```
This can only happen when there is a reference counting bug.

v2: fix typo

Signed-off-by: 
Reviewed-by: 
```
a7fb1e3a

drm/radeon: Prevent multiple debug error lines on suspend

Woody Suwalski authored 2 days ago


Fix to avoid multiple debug error lines printed on every suspend by Radeon driver's debugfs.

radeon_debugfs_init() calls debugfs_create_file() for every ring.

This results in printing multiple error lines to the screen and dmesg similar to this:

[   92.378726] debugfs: File 'radeon_ring_gfx' in directory '0000:00:01.0' already present!
[   92.378732] debugfs: File 'radeon_ring_cp1' in directory '0000:00:01.0' already present!
[   92.378734] debugfs: File 'radeon_ring_cp2' in directory '0000:00:01.0' already present!
[   92.378737] debugfs: File 'radeon_ring_dma1' in directory '0000:00:01.0' already present!
[   92.378739] debugfs: File 'radeon_ring_dma2' in directory '0000:00:01.0' already present!
[   92.380775] debugfs: File 'radeon_ring_uvd' in directory '0000:00:01.0' already present!
[   92.406620] debugfs: File 'radeon_ring_vce1' in directory '0000:00:01.0' already present!
[   92.406624] debugfs: File 'radeon_ring_vce2' in directory '0000:00:01.0' already present!

Patch v1: The fix was to run lookup() for the file before trying to (re)create that debug file.
Patch v2: Call the radeon_debugfs_init() only once when radeon ring is initialized (as suggested
by Christian K. - thanks)

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

ecc70403

drm/amd/display: add plane shaper TF support

Melissa Wen authored 4 weeks ago and Harry Wentland committed 1 day ago


Enable usage of predefined transfer func in addition to shaper 1D LUT.
That means we can save some complexity by just setting a predefined
curve, instead of programming a custom curve when preparing color space
for applying 3D LUT.

Reviewed-by: 
Signed-off-by:

562ec87c

drm/amd/display: add plane shaper LUT support

Melissa Wen authored 4 weeks ago and Harry Wentland committed 1 day ago


Map DC shaper LUT to DM plane color management. Shaper LUT can be used
to delinearize and/or normalize the color space for computational
efficiency and achiving specific visual styles. If a plane degamma is
apply to linearize the color space, a custom shaper 1D LUT can be used
just before applying 3D LUT.

v2:
- use DPP color caps to verify plane 3D LUT support
- add debug message if shaper LUT programming fails

v4:
- remove helper to check 3D LUT color caps (Harry)
- update desc of lut3d-setup helper from MPC to DPP

v5:
- remove color_mgmt_changed check that prevents color updates (Joshua)

Reviewed-by: 
Signed-off-by:

eb826a22

drm/amd/display: add HDR multiplier support

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 1 day ago


With `dc_fixpt_from_s3132()` translation, we can just use it to set
hdr_mult.

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

4ada44f0

drm/amd/display: add dc_fixpt_from_s3132 helper

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 1 day ago


Detach value translation from CTM to reuse it for programming HDR
multiplier property.

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

73370590

drm/amd/display: reject atomic commit if setting both plane and CRTC degamma

Melissa Wen authored 4 weeks ago


DC only has pre-blending degamma caps (plane/DPP) that is currently in
use for CRTC/post-blending degamma, so that we don't have HW caps to
perform plane and CRTC degamma at the same time. Reject atomic updates
when serspace sets both plane and CRTC degamma properties.

Reviewed-by: 
Signed-off-by:

b07cbca4

Revert "Revert "drm/amd/display: Adjust the MST resume flow""

Mario Limonciello authored 1 day ago

This reverts commit 1b3254b5

.

This issue was resolved by a dock firmware update, there is no
need to revert it.

Cc: Linux Regressions <[email protected]>
Cc: [email protected]
Signed-off-by:

55414dae

drm/amd/display: add plane degamma TF and LUT support

Joshua Ashton authored 4 weeks ago


Set DC plane with user degamma LUT or predefined TF from driver-specific
plane color properties. If plane and CRTC degamma are set in the same
time, plane degamma has priority.  That means, we only set CRTC degamma
if we don't have plane degamma LUT or TF to configure. We return -EINVAL
if we don't have plane degamma settings, so we can continue and check
CRTC degamma.

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

33ef40f6

drm/amdgpu: fix tear down order in amdgpu_vm_pt_free

Christian König authored 1 week ago


When freeing PD/PT with shadows it can happen that the shadow
destruction races with detaching the PD/PT from the VM causing a NULL
pointer dereference in the invalidation code.

Fix this by detaching the the PD/PT from the VM first and then
freeing the shadow instead.

Signed-off-by: 
Fixes: drm/amd#2867


Cc: <[email protected]>
Reviewed-by:

ff7eaa27

drm/amd/display: decouple steps for mapping CRTC degamma to DC plane

Melissa Wen authored 4 weeks ago


The next patch adds pre-blending degamma to AMD color mgmt pipeline, but
pre-blending degamma caps (DPP) is currently in use to provide DRM CRTC
atomic degamma or implict degamma on legacy gamma. Detach degamma usage
regarging CRTC color properties to manage plane and CRTC color
correction combinations.

Reviewed-by: 
Signed-off-by:

e319f2c5

drm/amd/display: mark plane as needing reset if color props change

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 1 day ago


We should reset a plane state if at least one of the color management
properties differs from old and new state.

Reviewed-by: 
Signed-off-by: 
Co-developed-by: 
Signed-off-by:

bb1bb3b0

drm/amd/display: set sdr_ref_white_level to 80 for out_transfer_func

Joshua Ashton authored 4 weeks ago


Otherwise this is just initialized to 0. This needs to actually have a
value so that compute_curve can work for PQ EOTF.

Reviewed-by: 
Signed-off-by: 
Co-developed-by: 
Signed-off-by:

a39a5a8d

drm/amd: include drm/drm_edid.h only where needed

Jani Nikula authored 2 days ago


Including drm_edid.h from amdgpu_mode.h causes the rebuild of literally
hundreds of files when drm_edid.h is modified, while there are only a
handful of files that actually need to include drm_edid.h.

Signed-off-by: 
Signed-off-by:

43591a49

drm/amd/display: add CRTC gamma TF support

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 2 days ago


Add predefined transfer function programming. There is no post-blending
out gamma ROM for hardcoded curves, but we can use AMD color modules to
program LUT parameters from pre-defined coefficients and an empty
regamma LUT (or bump up LUT parameters with pre-defined TF values).

v2:
- update crtc color mgmt if regamma TF differs between states (Joshua)
- map inverse EOTF to DC transfer function (Melissa)

v3:
- update AMDGPU TF list

v4:
- update comment regarding regamma behavior

Reviewed-by: 
Signed-off-by: 
Co-developed-by: 
Signed-off-by:

4c81f7de

drm/amd/display: encapsulate atomic regamma operation

Melissa Wen authored 4 weeks ago and Harry Wentland committed 2 days ago


We will wire up MPC 3D LUT to DM CRTC color pipeline in the next patch,
but so far, only for atomic interface. By checking
set_output_transfer_func in DC drivers with MPC 3D LUT support, we can
verify that regamma is only programmed when 3D LUT programming fails. As
a groundwork to introduce 3D LUT programming and better understand each
step, detach atomic regamma programming from the crtc colocr updating
code.

Reviewed-by: 
Signed-off-by:

ad12ccd9

drm/amd/display: add comments to describe DM crtc color mgmt behavior

Melissa Wen authored 4 weeks ago and Harry Wentland committed 2 days ago
```
Describe some expected behavior of the AMD DM color mgmt programming.

Reviewed-by: 
Signed-off-by: 
```
8ef1388c

drm/amd/display: add CRTC gamma TF driver-specific property

Melissa Wen authored 4 weeks ago and Harry Wentland committed 2 days ago


Add AMD pre-defined transfer function property to default DRM CRTC gamma
to convert to wire encoding with or without a user gamma LUT. There is
no post-blending regamma ROM for pre-defined TF. When setting Gamma TF
(!= Identity) and LUT at the same time, the color module will combine
the pre-defined TF and the custom LUT values into the LUT that's
actually programmed.

v2:
- enable CRTC prop in the end of driver-specific prop sequence
- define inverse EOTFs as supported regamma TFs
- reword driver-specific function doc to remove shaper/3D LUT

v3:
- spell out TF+LUT behavior in the commit and comments (Harry)

Reviewed-by: 
Co-developed-by: 
Signed-off-by: 
Signed-off-by:

13434618

drm/amd/display: add plane blend LUT and TF driver-specific properties

Joshua Ashton authored 4 weeks ago and Harry Wentland committed 2 days ago


Blend 1D LUT or a pre-defined transfer function (TF) can be set to
linearize content before blending, so that it's positioned just before
blending planes in the AMD color mgmt pipeline, and after 3D LUT
(non-linear space). Shaper and Blend LUTs are 1D LUTs that sandwich 3D
LUT. Drivers should advertize blend properties according to HW caps.

There is no blend ROM for pre-defined TF. When setting blend TF (!=
Identity) and LUT at the same time, the color module will combine the
pre-defined TF and the custom LUT values into the LUT that's actually
programmed.

v3:
- spell out TF+LUT behavior in the commit and comments (Harry)

v5:
- get blend blob correctly

Reviewed-by: 
Signed-off-by: 
Signed-off-by:

b2de717f

Dec 12, 2023

drm/amd/display: add plane shaper LUT and TF driver-specific properties

Melissa Wen authored 4 weeks ago


On AMD HW, 3D LUT always assumes a preceding shaper 1D LUT used for
delinearizing and/or normalizing the color space before applying a 3D
LUT. Add pre-defined transfer function to enable delinearizing content
with or without shaper LUT, where AMD color module calculates the
resulted shaper curve. We apply an inverse EOTF to go from linear
values to encoded values. If we are already in a non-linear space and/or
don't need to normalize values, we can bypass shaper LUT with a linear
transfer function that is also the default TF value.

There is no shaper ROM. When setting shaper TF (!= Identity) and LUT at
the same time, the color module will combine the pre-defined TF and the
custom LUT values into the LUT that's actually programmed.

v2:
- squash commits for shaper LUT and shaper TF
- define inverse EOTF as supported shaper TFs

v3:
- spell out TF+LUT behavior in the commit and comments (Harry)
- replace BT709 EOTF by inv OETF

v5:
- get shaper blob correctly (Joshua)

Reviewed-by: 
Signed-off-by:

e0cae980

drm/amdkfd: fix mes set shader debugger process management

jokim-amd authored 1 week ago


MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.

When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.

Normally, MES will purge its process context list when the last queue
has been removed.  The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.

If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.

On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation.  Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.

The solution is for KFD to explicitly flush the process context address
from MES on process termination.

Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.

Signed-off-by: 
Tested-by: 
Reviewed-by:

73204d02

Commits · amd-staging-drm-next · Alex Deucher / linux · GitLab

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