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[RISCV] Make zfbfmin imply the F extension

 1 year ago
source link: https://reviews.llvm.org/D151096
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Diff 524621

llvm/lib/Support/RISCVISAInfo.cpp

Show First 20 Lines • Show All 917 Lines • ▼ Show 20 Lines
static const char *ImpliedExtsV[] = {"zvl128b", "zve64d"};
static const char *ImpliedExtsXTHeadVdot[] = {"v"};
static const char *ImpliedExtsXsfvcp[] = {"zve32x"};
static const char *ImpliedExtsZcb[] = {"zca"};
static const char *ImpliedExtsZcmp[] = {"zca"};
static const char *ImpliedExtsZcmt[] = {"zca"};
static const char *ImpliedExtsZdinx[] = {"zfinx"};
static const char *ImpliedExtsZfa[] = {"f"};
+ static const char *ImpliedExtsZfbfmin[] = {"f"};
static const char *ImpliedExtsZfh[] = {"f"};
static const char *ImpliedExtsZfhmin[] = {"f"};
static const char *ImpliedExtsZfinx[] = {"zicsr"};
static const char *ImpliedExtsZhinx[] = {"zfinx"};
static const char *ImpliedExtsZhinxmin[] = {"zfinx"};
static const char *ImpliedExtsZicntr[] = {"zicsr"};
static const char *ImpliedExtsZihpm[] = {"zicsr"};
static const char *ImpliedExtsZk[] = {"zkn", "zkt", "zkr"};
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Lines
{{"v"}, {ImpliedExtsV}},
{{"xsfvcp"}, {ImpliedExtsXsfvcp}},
{{"xtheadvdot"}, {ImpliedExtsXTHeadVdot}},
{{"zcb"}, {ImpliedExtsZcb}},
{{"zcmp"}, {ImpliedExtsZcmp}},
{{"zcmt"}, {ImpliedExtsZcmt}},
{{"zdinx"}, {ImpliedExtsZdinx}},
{{"zfa"}, {ImpliedExtsZfa}},
+ {{"zfbfmin"}, {ImpliedExtsZfbfmin}},
{{"zfh"}, {ImpliedExtsZfh}},
{{"zfhmin"}, {ImpliedExtsZfhmin}},
{{"zfinx"}, {ImpliedExtsZfinx}},
{{"zhinx"}, {ImpliedExtsZhinx}},
{{"zhinxmin"}, {ImpliedExtsZhinxmin}},
{{"zicntr"}, {ImpliedExtsZicntr}},
{{"zihpm"}, {ImpliedExtsZihpm}},
{{"zk"}, {ImpliedExtsZk}},
▲ Show 20 Lines • Show All 197 Lines • Show Last 20 Lines

llvm/test/MC/RISCV/attribute-arch.s

Show First 20 Lines • Show All 258 Lines • ▼ Show 20 Lines
# CHECK: attribute 5, "rv32i2p1_zicond1p0"
.attribute arch, "rv32i_smaia1p0"
# CHECK: attribute 5, "rv32i2p1_smaia1p0"
.attribute arch, "rv32i_ssaia1p0"
# CHECK: attribute 5, "rv32i2p1_ssaia1p0"
- .attribute arch, "rv32if_zfbfmin0p6"
+ .attribute arch, "rv32i_zfbfmin0p6"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfbfmin0p6"
.attribute arch, "rv32i_zvfbfmin0p6"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfmin0p6_zvl32b1p0"
.attribute arch, "rv32i_zvfbfwma0p6"
# CHECK: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zve32f1p0_zve32x1p0_zvfbfwma0p6_zvl32b1p0"

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