Intel Unveils 3rd Gen Ice Lake-SP Xeon CPU Family: 10nm+ Sunny Cove Cores, New Instructions, 28 Core Chip Showcased

The 2nd-Generation Intel Xeon Scalable platform provides the foundation for a powerful data center platform that creates a leap in agility and scalability. Intel Corporation on April 2, 2019, introduced a portfolio of data-centric tools to help its customers extract more value from their data. (Credit: Intel Corporation)

Intel has unveiled the details of its next-generation Xeon CPU family codenamed Ice Lake-SP at HotChips 32. Coming later this year, Ice Lake-SP CPUs are going to host a range of new features such as a brand new chip architecture, improved I/O, and an enhanced software stack powering Intel's first 10nm server lineup.

Intel Ice Lake-SP 'Next-Gen Xeon' CPUs Detailed - Feature 10nm+ Sunny Cove Cores & Advanced Capabilities

The Intel Ice Lake-SP is officially launching later this year on the Whitley platform. The platform will scale to single and dual-socket servers. In its presentation, Intel unveiled a 28 core Ice Lake-SP CPU as an example to demonstrate the enhanced capabilities that Ice Lake-SP offers over Cascade Lake-SP.

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Intel has not confirmed if the 28 core CPU they showcased is the highest core count that will be available with the Ice Lake-SP family or if there would be higher core count variants. Earlier rumors do point to higher core counts so this 28 core die could just be used for comparison with the top of the stack 2nd Gen Xeon CPUs available today.

Intel Ice Lake-SP 'Next-Gen CPU' CPU Architecture

Coming to the details, Intel mentions that its Ice Lake-SP CPUs are fabricated on the 10nm+ process and not the 10nm++ process which is utilized by the Tiger Lake CPUs which launch next month. The Ice Lake-SP family will make use of the Sunny Cove cores which deliver up to 18% IPC increase over the Skylake architecture which all 14nm Xeon CPUs utilize.

Intel's 3rd Gen Xeon Scalable Family, Codenamed Ice Lake-SP, presentation at HotChip 32 (Image Credits: HardwareLuxx)

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The Sunny Cove architecture, in general, adds a range of improvements over Cascade Lake or the enhanced Skylake cores such as:

• Improved Front end: higher capacity and improved branch predictor
• Wider and deeper machine: wider allocation and execution resources + larger structures
• Enhancements in TLBs, single-thread execution, prefetching
• Server enhancements - larger Mid-level Cache (L2) + second FMA

Intel also adds in a range of new SIMD instructions exclusive to the Sunny Cove server processors that are mainly meant to increase performance in Cryptography and compression/decompression workloads. That along with enhanced software and algorithmic support will allow Intel gains of up to 8X per core over Cascade Lake.

Intel Xeon SP Families (Preliminary):

Intel Ice Lake-SP 'Next-Gen CPU' 28 Core Die & Whitley Platform Detailed

Looking at the block diagram of the Ice Lake-SP 28 core CPU, the chip offers a new interconnect in the form of an enhanced Mesh Fabric which runs through all of the 28 CPU cores. The Ice Lake-SP die features two 4-channel memory controllers whereas the Cascade Lake-SP die offered two tri-channel memory controllers.

The Intel Ice Lake-SP processors also feature four PCIe Gen 4 controllers, each offers 16 Gen 4 lanes for a total of 64 lanes on the 28 core die. The Cascade Lake-SP chips offered hexa-channel memory support while Ice Lake-SP will offer octa-channel memory support on the Whitley platform at launch. The platform will be able to support up to DDR4-3200 MHz memory (16 DIMM per socket with 2nd Gen persistent memory support.

Intel is also adding a range of latency and coherence optimizations to Ice Lake-SP chips. But you can see that the memory bandwidth-latency gets a big jump with the 8-channel memory interface and the higher DIMM speeds.

Intel Ice Lake-SP 'Next-Gen CPU' New Interconnect Infrastructure

In addition to the standard Mesh interconnect, Intel has further expanded its interconnect design for Ice Lake-SP Xeon CPUs. The new control fabric and data fabric do connect with the cores and different controllers of the chip but also manage the data flower and power control for the chips themselves. These new interconnects will deliver even lower latency and faster clock updates than 3rd Gen Cooper Lake-SP chips. For example, the core frequency transition takes 12us and the mesh frequency transition takes 20us on Cascade Lake-SP chips. Ice Lake-SP in comparison takes less than 1us and 7us, respectively.

The less frequency drain means higher efficiency over Cascade Lake. Ice Lake-SP will also improve upon the AVX frequency since not all AVX-512 workloads consume higher power. This also isn't specific to just AVX-512. Even AVX-256 instructions on Ice Lake-SP will deliver better frequencies profile over Cascade Lake CPUs.