How do engineers deliver 10 defective parts per billion (Dppb) to auto makers if they only screen 1 million parts per year? Answer: By comprehending failure mechanisms and proactively screening for them.

Modern automobiles contain nearly 1,000 ICs that must perform over the vehicle’s life (15 years). This drives quality expectations ever higher. While 10 Dppm used to be a solid benchmark, the bar is now 10 Dppb (10 ppm = 10,000 ppb). This change is driving enormous engineering R&D efforts to screen nuanced test escapes and to remove more potential reliability failures.

Over the past five years, both product engineers and inspection equipment suppliers have developed novel test methods and inspection capabilities that help bring the 10 defect Dppb objective within reach. These solutions address both semiconductor device and assembly failure mechanisms. (This article solely focuses on semiconductor device defects.)

All of this needs to be set in the context of the different semiconductor processes used for the auto industry. A high percentage of automotive ICs are analog or mixed-signal components, which are manufactured on mature technologies and have larger minimum feature sizes. The mature technologies used in cars have been meeting the 10 Dppm target for quite some time, and their ASPs are significantly lower than those of complex SoCs, which are developed at 22nm and smaller nodes. Moving from 10 Dppm to 10 Dppb presents a significant engineering cost challenge.

“Quality-sensitive customers who can ill afford having any test escapes will be willing to trade off yield for ensuring only the highest quality devices ship to their end customers,” said Guy Cortez, product marketing manager in Synopsys’ Digital Design Group. “Automotive, medical and datacenters are several verticals where quality is still very important.”

Due to the computing demands of enabling ADAS capabilities, and of handling the growing number of electronic sensors, auto makers now require large SoCs on advanced CMOS processes.

“Quality and reliability are becoming even more important when advanced node semiconductors are finding themselves driving mission- and service-critical applications, with zero tolerance for downtime and faults, like in data centers and automotive,” said Nir Sever, senior director of product marketing at proteanTecs.

Advanced-node SoCs contain hundreds of millions of transistors and include billions of vias connecting polysilicon-to-metal and metal-to-metal layers.

“It’s not just parts per billion per wafer, with all these vias,” said Andrzej Strojwas CTO at PDF Solutions. “You really need to evaluate parts per billion right now with the current chips. If you want to use wafer-level inspection, the relevant numbers are ppb or fractions of ppb. With optical you cannot afford to inspect every wafer layer. In addition, for a lot of defects that are relevant right now, they are buried. You cannot see them with optical.”

That high expectation requires constant innovation across the fab’s inspection and testing operations for automotive components. As always, to reduce escapes, engineers first turn to die and unit level manufacturing test. Adding a new test pattern can screen a customer return. For reliability failures, applying a high-voltage stress test obviates the need for an expensive burn-in process.

A new logic cell fault model
In their 2021 International Test Conference paper, NXP automotive engineers shared their new test patterns to screen subtle at-speed defects. An investigation of automotive customer returns identified the physical root cause to be a PMOS source contact missing its silicide film, which increased resistance and impacted the delay of the gate. This behavior was not screened by any existing digital delay fault model. This subtle defect behavior is unfortunately never observed because existing ATPG applied fault models assume single-input switching.

“One case to exemplify this problem could be two input XOR/XNOR gates, which might not generate a logical transition at the output if both inputs change at the same time. Yet, in presence of a delay defect, a delayed transition might appear at output, which could cause a timing violation, leading to malfunction,” the authors explained. “To generate a test that will expose this defect, we need to have a stimulus that will target concurrent transition of the inputs. The same test quality gap can be observed in other gates. It is especially noticeable that in lower geometries, Miller capacitance is dominant, which causes delay difference between input-to-output with other inputs static vs. other inputs toggling at the same time.”

By creating a new fault model, the Multi-Transition Fault Model (MTFM), and identifying high-risk standard cells to apply this model, the engineering team deployed new patterns to automotive ICs. Over one year, the team reported production test results on two high-volume automotive designs with MTFM patterns. Unique fallout from about 9 million parts was measured at about 5 Dppm or 5,000 Dppb.

High Voltage stress for finFET
Engineers continue to use testing to screen for latent defects that can adversely impact a circuit’s reliability. Latent defects can exist in the form of partial metal lines, metal stringers, or gate oxide pin holes. While burn-in stress of packaged die can accelerate these defects to exhibit failing behavior, for automotive ICs this costly manufacturing step can be skipped by employing a wafer level electrical stress instead.

Fig. 1: Examples of killer and latent defects. Source: KLA

A high voltage stress tests (HVST) accelerates latent defects, which are then detected with a production test. Reliability engineers recommend using dynamic voltage stress (DVS) in which internal nodes toggle their states, and an enhanced voltage stress (EVS) in which internal nodes keep the same value.

The introduction of finFET CMOS devices to automotive ICs presents a new yield/quality/cost triangle challenge to engineers applying HVST. In sharing their solution in an ITC paper, NXP automotive process engineers noted, “With introduction of product designs on finFET technologies, fundamental device physics characteristics…have a major contribution to static leakage consumption at the elevated voltage stress conditions. This exposes unique challenges on how to perform HVST effectively and efficiently on finFET technologies.”

These challenges included:

• Observing a per-die high variability in static leakage at elevated voltages, maintaining 8X to 32X parallelism during wafer probe;
• Inadvertently triggering ATE current clamp limits, and
• Balancing product quality impact of too low a voltage stress with product yield impact of too high a voltage stress.

In response, the engineering team applied an innovative adaptive test approach to two different EVS limits based upon IDD static leakage measurements. “It dynamically adjusts HVST stress voltage based on real-time current measurement to ensure every part is stressed reliably at the highest possible voltage within the tester hardware current limit, as well as with equivalent extrinsic defect coverage,” they wrote. “In this way, it can achieve the desired test cost, product margins and hardware budget, without risking product quality.”

With characterization for a specific process node, process reliability engineers arrived at the two EVS limits. Determining the static IDD leakage current limits needs to be based upon a product characterization method. The engineering team evaluated their HVST methodology on NXP 16nm finFET products and reported no current clamping occurred during HVST.

Wafer inspection
One of the key drivers behind 100% wafer inspection at critical layers during manufacturing is the need to achieve sufficient quality. Only high-speed inspection systems are capable of meeting such high productivity goals in the fab. Both optical- and E-probe-based systems are enabling automotive IC suppliers to identify subtle defects that might otherwise escape electrical test.

Optical inspection, in the form of brightfield and darkfield exposures, remains the most commonly used production inspection technique. Each has its strong points. Brightfield inspection excels in detecting flat defects or in-trench defects between structures, while darkfield excels at detecting scattering defects on top of structures.

KLA engineers separately collaborated with OnSemi and NXP engineers to explore how to leverage inspection data on automotive IC parts for identifying reliability failures. These collaborations drove the application of outlier detection techniques to inspection data. The engineering teams initially reported their pilot studies at the 2019 Automotive Electronic Council Workshop on Reliability. In a 2020 SPIE paper, KLA engineers described the outlier detection methodology, Inline Defect Part Average Testing (I-PAT), and summarized the pilot study results.

“By itself, process control methods cannot decide if individual die are healthy,” said Jay Rathert, senior director of strategic collaborations at KLA. “But the advent of high-speed inspection screening with I-PAT is creating an inflection point, powered by advanced computing power, image processing algorithms and machine learning. Screening with I-PAT looks at 100% of die and 100% of wafers on a few reliability-critical layers. Bringing outlier recognition methods to the defect domain, each die’s defectivity can now be compared to a larger population to quantify its relative reliability risk.”

Fig. 2: Manufacturing controls, inspection screens, and electrical test flow. Source: KLA

The NXP/KLA feasibility study used historical data from about 250,000 die (600 wafers, with about 400 dies/wafer) and they correlated I-PAT defectivity scores to electrical test including sort yields, die bins, parametric values, and post burn-in failures. Thresholds for I-PAT scores can be applied in both a static or dynamic assessment of defectivity per die. Results from the I-PAT and wafer test result comparison showed that a percentage of wafer failing die would fail a I-PAT threshold. I-PAT defectivity scores also identified some unique die, and these represent potential test escapes or latent-reliability failures.

To minimize failing good die (a.k.a. overkill) the OnSemi/KLA team described how they applied two data filters to defectivity data prior to I-PAT analysis. The first filter identified only defects in a design critical area (physical layout analysis of defect sensitivity). A second filter used the inspection layer in which defect was detected and sized with detection mode (darkfield/lightfield) exposure. Combined, these two filters reduced overkill by 90%. After filtering, the data was run through the I-PAT methodology, which the KLA SPIE authors described as follows:

“The I-PAT methodology uses an advanced correlation engine to weight defect probability based on defect inspection attributes … Inspection attributes include defect size, location, polarity, detection channel, cluster, etc. The method invokes an intelligent and adaptive machine learning (ML) model to assign each defect an accurate classification. Defects are then weighted based on their impact to device reliability. Of paramount importance is the appropriate assessment of ground truth indicators to validate the classification and weighting. The impact of all the defects are then aggregated to provide an overall defectivity score for each die. These die-level defectivity scores are then filtered using statistical outlier methods analogous to the PAT methods used in electrical test screening.”

Fig. 3: I-PAT methodology components. Source: KLA

With SEM imaging, the OnSemi engineers verified that I-PAT identified unique die contained latent defects.

Probing for buried via defects
E-beam offers different measurement capabilities than optical. In particular, voltage contrast enables engineers to detect sub-surface defects that exist in contacts and vias. PDF Solutions has tuned an E-beam probe system to perform voltage contrast measurements using a vector scanning mode focused on problematic layout structures.

“If you look at the E-probe tool itself, one of the big reasons why we built it as a vector scanner is we connected the overall DirectScan methodology to layout analysis. You can basically take the critical layers with the riskiest patterns, or the patterns that the diagnostic tool picks up as things that are going wrong,” said PK Mozumder, vice president for leading edge at PDF Solutions. “You can run the vector scanner to hit just those points, and basically within two hours you can get ppb-level resolution. So now it becomes a manufacturing tool that you can use in production to do non-destructive disposition effectively.”

Identifying the risky layout patterns to probe requires pre-work before the mask sets are even created. Determining a design’s problematic layout structures informs design and placement of design for inspection (DFI) filler cells. These are placed in very close proximity to the actual design’s cell layout using empty space between cells. The E-beam system takes measurements on metal pads found in the DFI filler cells. As a result, a product wafer can have billions of DFI filler cells, which naturally provides parts per billion measurement resolution.

Fig. 4: Tying vulnerable layout patters to E-probe scan of DFI. Source: PDF Solutions

The e-beam probe measurement then can be used to identify voids, shorts and potential reliability defects. In a NANOTS 2021 paper, PDF Solutions engineers described this measurement capability:

“Opens are detected when a DFI Fill cell pad for an open-fail mode turns dark. When no defect is present, the pad will be bright due to the secondary electrons emitted when a path to ground is present. Shorts are detected when a DFI Fill cell pad turns bright. The DFI system is able to measure ‘gray-scale’ levels corresponding to soft shorts or leakage currents – we refer to this as the DFI Electrical Response Index (ERI). In order to calibrate the gray scale levels to electrical leakage magnitudes, DFI test structures were placed in the scribe that enabled measuring electrical leakage and DFI ERI on the same test structure.”

Fig. 5: E-beam probe using voltage contrast dark image indicates an open. Source: PDF Solutions

The ability to include the grey cell between the black and white cells of bad to good dies provides choices for engineers for the next manufacturing test steps. Furthermore, this e-beam measurement data complements electrical test data, which will detect some of these soft defects. The ones with a large leakage will fail electrical test, but the ones with small leakages escape electrical test and eventually can fail in the field.

“Nonetheless, you still want the benefit of test data, because then you know what signals you’re getting over and above beyond what’s popping out from test. There’s going to be some vulnerabilities that are going to become evident in your test signatures,” said Marcin Strojwas, general manager for design for manufacturability at PDF Solutions. “Then, just due to the nature of these leakages, there is going to be some that are just below the threshold of what you’d be able to detect in test at time zero.”

Combining wafer inspection with test data
In the past decade, engineers have been using different data sources in new combinations to perform root-cause yield excursions, but also to optimize wafer, assembly and test factory operations by identifying quality issues earlier. Inspection data — optical, interpolated wafer maps, e-beam — can be combined with electrical screening to identify potential test escapes and reliability-related failures (latent defects).

“A key driving force to combine these disparate data sources today is the effort to stop the escape of low reliability devices into the automotive supply chain, where mission-critical or safety-critical failures may occur. It is well understood by the industry that test is unable to recognize and stop every bad die, so escapes do occur even with extremely high levels of test coverage,” said KLA’s Rathert. “When car manufacturers use devices from newly released nodes, where yields are lower, the problem is worse. And the statistical likelihood of such escapes is orders of magnitude higher than the desired part-per-billion requirements specified. New methods are needed to augment the decision of which dies are fit for purpose.”

Scratch detection, from macro to micro defects
Scratches on wafers can ripple into die-level reliability failures. By combining wafer test data and 100% wafer inspection at specific layers, engineers can increase the detection of scratches. In an Advanced Semiconductor Manufacturing Conference 2021 paper, an engineering team from SkyWater Technology Foundry and Onto Innovation described their focus on wafer scratch detection:

“As scratch patterns are unique and critical to detect accurately, we realized that we needed to go beyond standard scratch detection algorithms provided by SPR Engine. Therefore, we built an additional post processing algorithm dedicated to run image-based scratch detection instead of defect-based detection using dynamic threshold determination (based on density and distribution) to eliminate or reduce false positives.”

Fig. 6: Image-based wafer scratch detection builds on defect-based detection. Source: Onto Innovation

Identifying scratches leads to identification of potential reliability failures. A die with a scratch or its neighbors may pass wafer test yet can fail at unit-level testing or out in the field. Why is that?

“Physically, wafer scratches can be dense or thin. They can be indictive of a micro-crack. And due to material physics when the wafer is diced this scratch/crack will proliferate either to the edges of the effected die and/or to neighboring die. Those neighboring die represent reliability failures,” said Prasad Bachiraju, director for sales and customer solutions at Onto Innovation. “Especially in automotive, when they detect these types of failures [SiC scratches], they don’t want to take any risk. So they will fail die within two millimeters of the scratch.”

Latent defects on mature mixed-signal IC
Mixed-signal/analog devices dominate automotive electronic control units (ECUs) and they are manufactured on very mature semiconductor processes. Yet these IC suppliers also need to move from 10 Dppm to 10 Dppb quality objective. In a European Test Symposium 2020 paper OnSemi engineers and Katholic University researchers explored combining die inspection data with per die electrical test data to enhance dynamic part average testing. Called Visually-Enhanced DPAT, (VE-DPAT), their goal was to screen out subtle latent defects not detected by Dynamic PAT, with little to no yield loss.

The engineering team investigated combining the two data sources with multiplication. They described it the new metric follows.

“The screening parameter αA,Di is constructed as the multiplication of two standardized numbers and gives as a result a standardized number. This formulation was chosen for its advantageous properties. It can be used across different specifications, going from leakage measurements expressed in nano-amperes to oscillation frequencies expressed in MHz. The general interpretation of these two standardized numbers can almost be considered as the probability of having a defective device.”

Others a terms of standardized values, outlier detection rate is significantly improved as well as easier to implement during production test.

Regarding the pass/fail limits they wrote “After the calculation of the screening parameter αA,Di for a measurement A, the die Di is considered as an outlier if the value αA,Di exceeds the detection threshold TH chosen by design. In practice, a die Di is attributed a series of outlier parameters αA,Di, i.e., one for each layer where a defect was found, combined with each measurement for which the outlier method was activated.”

The straightforward multiplication can result in defects with uncorrelated electrical deviations which results in unnecessary yield lost. To refine the multiplication, they used a designer engineer’s knowledge of layout, defect size and potential correlation to an electrical test.

The OnSemi/KU team evaluated the VE-DPAT metrics on a boost double-buck LED driver (used for automotive lighting applications 60V and 1.6 amp) manufactured in 0.35µm bipolar CMOS DMOS (BCD) technology. Data was collected from 25 wafers over 5 lots, and the data included inspection at 7 wafer manufacturing steps and about 400 electrical tests per die. In applying the first multiplication method for various detection threshold values they reported an additional 1% rejection when TH equaled 4, and 0.1% rejection when TH equaled 10. They further shared this metric uniquely found an impactful defect described as “a discoloration on a large DMOS of an output driver which correlates with an abnormal current leakage on the same DMOS.”

Conclusion
Engineering teams are making great strides in meeting automotive makers’ exceedingly stringent quality objective of 10 Dppb. The methods engineers choose to deploy will correspond to the semiconductor technology maturity and a product’s ASP. With the wide range of semiconductor technologies found in vehicles, one can expect a wide range of solutions. Engineers must simultaneously ferret out subtle defects while keeping costs minimal — measured in cents and 0.01% yield loss. Because in automotive, while quality is paramount, so is the need to maintain supplier profitability.

Related Stories

Research/References
S. Traynor, C. He, Y. Y. Yu and K. Klein, “Adaptive High Voltage Stress Methodology to Enable Automotive Quality on FinFET Technologies,” 2021 IEEE International Test Conference (ITC), 2021, pp. 289-293
https://ieeexplore.ieee.org/document/9611339

J. Corso, S. Ramesh, K. Abishek, L. T. Tan and C. Hooi Lew, “Multi-Transition Fault Model (MTFM) ATPG patterns towards achieving 0 DPPB on automotive designs,” 2021 IEEE International Test Conference (ITC), 2021, pp. 278-283
https://ieeexplore.ieee.org/document/9611352

All presentations from 2019 Automotive Electronics Council Reliability Workshop can be found at this link: http://www.aecouncil.com/AECWorkshop.html

Anilturk, O. et al., “Inline Part Average Testing (I-PAT) to Reduce Escapes from both Gaps in Test and Latent Reliability Defects: Continuing Feasibility Study Results at NXP,” Anilturk, Second European Automotive Electronics Council Reliability Workshop, Oct. 15, 2019.

Bruneel, G. et al., “Implementation of I-PAT Using High Speed Defect Screening,” Second European Automotive Electronics Council Reliability Workshop, Oct. 15, 2019.

John C. Robinson, Kara Sherman, David W. Price, Jay Rathert, “Inline Part Average Testing (I-PAT) for automotive die reliability,”
Proceedings Volume 11325, Metrology, Inspection, and Process Control for Microlithography XXXIV; 113250D (2020) https://doi.org/10.1117/12.2551539
Event: SPIE Advanced Lithography, 2020, San Jose, California, United States
https://www.spiedigitallibrary.org/conference-proceedings-of-spie/11325/113250D/Inline-Part-Average-Testing-I-PAT-for-automotive-die-reliability/10.1117/12.2551539.short

Marcin Strojwas, et al. “Advanced High Throughput e-Beam Inspection with DirectScan,” NANOTS 2021 Conference.
https://www.pdf.com/resources/nanots-2021-advanced-high-throughput-e-beam-inspection-with-directscan/

D. Gross, K. Gramling and P. L. Bachiraju, “Fab Fingerprint for Proactive Yield Management,” 2021 32nd Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC), 2021, pp. 1-4.
https://ieeexplore.ieee.org/document/9435686

A. Coyette, W. Dobbelaere, R. Vanhooren, N. Xama, J. Gomez and G. Gielen, “Latent Defect Screening with Visually-Enhanced Dynamic Part Average Testing,” 2020 IEEE European Test Symposium (ETS), 2020, pp. 1-6.