One of the most heavily researched and lauded emerging memory technologies is ReRAM. A low power, non-volatile option, ReRAM has found applications in many fields, including in-memory computing and neuromorphic computing.

The general construction of ReRAM memory. Image used courtesy of Weebit Nano

This week, Weebit Nano announced that it had demonstrated its first crossbar ReRAM arrays, a significant milestone for the company and the technology. 

In this article, we’ll take a look at challenges in scaling ReRAM technology as well as Weebit Nano’s newest breakthrough.

Scaling Issues with 1T1R

One of the most popular techniques for creating ReRAM cells today is using the 1T1R (one transistor, one resistor) architecture. 

The basic structure of this architecture consists of a single pass transistor for accessing the cell for read and write operations, along with a single resistive storage element for storing bits. 

The 1T1R structure has been a popular choice for many reasons. First, the architecture is similar to a dynamic random-access memory (DRAM) cell, making design and use intuitive and understood. 

Beyond this, the pass transistor helps isolate current to the cells and meet the demand for high-speed memory technology.

The basic structure of a 1T1R ReRAM cell. Image used courtesy of Meena et al

However, the largest downside of the 1T1R architecture is that it is not sufficient to support the large arrays of memory cells needed for discrete memory chips. 

For starters, the size of the 1T1R cell is constrained by the access transistor, posing a challenge to creating high-density ReRAM cells. 

On top of this, the non-trivial leakage current of transistors at smaller nodes is becoming a major problem for power density and efficiency.

With these drawbacks in mind, let's take a look at Weebit Nano's latest ReRAM arrays.

Weebit Nano’s ReRAM Arrays

This week, Weebit Nano announced that they could successfully sidestep the 1T1R challenges and develop a crossbar (high density) ReRAM array.

To avoid the challenges posed by the 1T1R architecture, Weebit Nano instead opted to employ a one selector one resistor (1S1R) architecture. 

In this architecture, the access transistor is replaced by a "selector," the nature of which is not currently disclosed. In the past, researchers have used ovonic threshold switch (OTS) selectors in place of transistors with high levels of success.

Structure of the 1T1S crossbar array. Image used courtesy of Weebit Nano

In general, OTS selectors have offered small features, a simple structure, high switching speed, and low energy consumption. 

On top of this, they eliminate the leakage current present in a pass transistor. For these reasons, we can make an educated guess that Weebit Nano is following a similar trend.

By using a selector in place of a pass transistor, Weebit Nano claims that they could develop a 1S1R crossbar array that can be stacked in 3D layers, achieving extremely high densities. 

Moving forward, Weebit believes its 1S1R crossbar ReRAM architecture has potential applications in storage-class memory, persistent memory, as a NOR flash replacement, in-memory computing, and neuromorphic computing.

Taking ReRAM to the Next Level

A major step for Weebit Nano and ReRAM technology, the development of Weebit's crossbar array holds many promises to the future of memory technology. 

Hopefully, enabling higher density ReRAM offerings, Weebit Nano's technology could impact the future of non-volatile memory. 

It will be interesting to see where Weebit Nano takes its memory solution and see what other innovations start picking up the pace to further ReRAM technology. 

Interested in other memory innovations? Read on in the articles down below.

Three New Memory Technologies Keep Pace With Computing Demands

New Research Suggests Processing-in-Memory Could Revolutionize Analog Computing

Phase-change Memory Could Open Doors to Better Data Storage and Computing