THis is interesting research, but this is hardly the first non-von neumann machine. In fact we give the popular architecture (single address space) a name specifically to distinguish it from the harvard architecture (split I/D space).  You could argue that the microarchitecture of modern CPUs is a kind of harvard architecture in fact.

I seem to remember one of the minor members of DEC's PDP line had a split I/D space but didn't see it on the wikipedia.

Alo there was a lot of experimentation in the 80s on different architectures (e.g. dataflow) -- one was even named "non-von"

Yes there have been many other attempts to buid non von Neumann computers, but DARPA claims they have all failed. They also claim they will keep working on it until they succeed because it is a "Hard-to-Do: Must Do" to solve Big Data.

The Atmel AVR is a failure?  That's news to me!

Memory access time has been key ever since computers were invented.  It looks like they think that access time is inversely proportional to data width.  It is the time to access the first byte that is the killer -- the streaming time for the remaining data is overlapped with the access time for the next access, therefore hidden.

Too bad the focus is not on the real problem based on distance and speed of light.

@dvhw:  Could you please explain why the AVR is non von?  It looks like just another RISC because only loads and stores access memory for data, and of course I fetches are from memory.  It sure looks like both data and instructions are in the same memory.

@Karl ...It sure looks like both data and instructions are in the same memory.

The AVR is Harvard architecture. See the following web site...

http://www.avr-tutorials.com/general/avr-memory-map

The 8051 is also Harvard architecture.

You are right. DARPA agrees that it is a memory access time problem--in particular random access time of 8-byte data points. DARPA claims that today's processors fill large caches quickly, but the sparse packing of relevant Big Data is in the 8-byte range making the moving of large blocks a waste of energy. Beside parallel access to global memory, it has added independent scratch pad memories to all cores so they can simultaneously grab 8-byte data points from global memory, process them in local memory, return their results and repeat.

DRC computer show a fpga based graph processor at SC 20115.

https://youtu.be/DZZuur8LXOY

Darpa can just go out buy stuff instead of paying big bucks to have someone reinvent the wheel.

@Elizabeth:  Thanks.  The memory map explains it well.  Harvard was used a lot because the program was in ROM, therefore could not store variable data.  

Even the x86 had some kind of control bit that separated data from instruction.  That is until JIT compiled into data cache then triggered an instruction cache update.

Are we sure that DARPA knows what they are doing?

Those kinds of memory access speeds/patterns seem extremely high. Any idea how they will get there ?

@Colin:  Pre System/360 high end IBM CPUs had data buffers to try to speed up matrix inversion.

Model 85 introduced cache as an improvement.  Meanwhile Models 350 65 and 75 had 4 way interleaved memories which gave the ability to have multiple(up to 4) 8 byte accesses depending on the low order 2 bits of the address.

The address decoding steered the request to individual memory arrays and then delivered the returned 8 bytes to each requester.

Your reply makes me think that there will be many memories multiplexed in some fashion over an ultra high speed link/bus.  That seems fair.  Thanks, that brought back memories about memories.

P.S. Cache was for calculation intensive apps, not random accesses.

Also earlier CPUs had 2 way interleave so there could be an instruction fetch and a data access to allow instruction decode to be overlapped with execution of the previous instruction.

Elizabeth already memtiond 2 Harvard(non von) examples after DARPA SAID all non-vons failed.  Now I picked up on this:

HIVE is not von Neumann because of the sparseness of its data and its ability to simultaneously perform different processes on different areas of memory simultaneously," Trung said. "This non-von-Neumann approach allows one big map that can be accessed by many processors at the same time, each using its own local scratch-pad memory while simultaneously performing scatter-and-gather operations across global memory."

It so happens that NASA moon shot control center in Houston had a cluster of 4 360 Model 75s with IO channels that could do scatter/gather, but that did not make them non-von.

Cache was simply not available when the control center was built.  Also the CPUS were CISC (not superscalar RISC) as that nonsense had not come about yet.

So DARPA wants a bigger better faster IMPROVED system for a different application.  Steve pointed out that even the application is not totally new.

Yes, that bothered me too, thanks for bringing it up. DARPA did the research and found what it calls attempts to create non-von-Neumann architectures and decided that they were not successful. By what metric they measured "success" Trung did not say, and the BAA does not specifically call for a non von Neumann solution (we'll have to wait and see what Intel and Qualcomm propose as architectures, the examples given were just to clarify the problem). After speaking with Trung, I believe his measure of success is "widely popular" as they pitched to Intel and Qualcomm that if they create a non von Neumann architecture that cuts through Big Data like a knife through buttter and thus becomes widely popular, then HIVE will become known as the first, even though there were previous attempts. DARPA wants to create unique firsts that become widely popular, like the Internet, even though there were previous networks before Arpanet. DARPA justifies its existence by the value they give to civilian society after satisfying their military goals with the same technology.

Thanks, Colin:  I wish we knew more about Microsoft's "FPGA in the cloud"(evolution from project Catapult) because they may be working on a similar problem.

Another aspect is that CPU ISAs infer that all data is in memory and there must be 2 loads, an assign, and a store(4 instruction fetches, 2 data fetches, and a data store -- just to add 2 numbers.  Again Microsoft Research "Where's the beef" compared FPGA to CPU and concluded that there are too many instruction fetches.

I believe that a new processor that does if/else, for, while, do, and assignments while keeping variables local is doable by using the Roslyn/CSharp parser APIs.  (I am in the process of doing it)

Thanks Karl. I'm sure you'll picque some interest in those Roslyn/CSharp parser APIs.

I would like to point out the first non-von Neuman comuter architecture was a Meta-Mentor. Patented in 2006, the architecture earased the differences between von Neuman and Harvard architectures by splitting the functions into two distinct parts. It is also referred as Multi Domain Architecture (MDA).  It uses combinational mathematics to determine faults and prevent computer viruses. For example, using Byzantine mathematics, the number of systems required to detect a fault is: n >= 3m +1.  (n = number of systems, m = number of faults) This means using von Neumann architecture, a minimum of four systems are required to detect and recover from a single fault. Using Combinatorial techniques like Greaco-Latin squares, or even Latin squares, MDA needs a maximum of three reconfigurable systems.  That is, three MDA systems can detect up to three different types of faults, and remain functioning and fault tolerant after the failures. This is just one of its features.

Roger Smith

Even if I already thought of a computer were processing power could be distributed near memory areas, one must reckon that some sequences of code would generate a single instruction fetch for an addition, because both inputs and output all live in registers. Sure, this does apply only under favorable circonstances, but with right CPU, compiler and compiler options, it happens enough that have count of instruction fetches to be noticeably decreased

Previous attempts in the late 1980s and 1990s at pushing  non-von-Neumann architectures such as Lisp machines, data flow machines, and reduction machines all failed to gain acceptance in the marketplace. While such designs had a strong intellectual appeal among the research community, they would have required the wholescale adaption of programming paradigms that are foreigng to  most developers and the OS and every application needs to be  rewritten in these paradigms. Had advances in traditional processors stalled the cost may have been deemed acceptable, but the big chip makers poured resources into fabrication techniques and deeper super scaler pipelines that allowed the old dusty deck of C porgrams to run faster and faster and consequently non-von-Neumann architectures got the reputation as impractical.

@sw guy:  I think you mean that data fetches are reduced, because  instruction fetches specify which data operands to use even if they are in register files.

@Colin:  There is zero chance of any interest.

1) It runs on "Windoze".

2) Not RISC 

3) Not Linux

4) No TCL scripting

5) Not from an EDA vendor

6) Not based on marketing hype and buzz words

@KarlS01

Here is what I meant, using fantasy instruction set.

You said the sequence for a single addition is:
load  REG1,DATA1
load  REG2,DATA2
add   REG3,REG1,REG2
store REG3,RESULT
(4 instructions fetch)

But as soon as optimizer is able to go full steam ahead, actual sequence would be:
add   REG3,REG1,REG2

Of course, some load ahead and some store behind are needed, but some compiler are very smart are getting rid of memory storage for local variable, which may be awkard to debug but is good for:
- Program size
- Data set size
- Count of instructions to get same work done
(abstract: good for performance from every side)

"Of course, some load ahead and some store behind are needed..........."  And it also depends on omputation intensive applications, not general applications where the control flow is full of branches.

This is the falacy of super scalar assumptions that there is very high probability that the data has been put in a register previously.  Can you quantify "some" in some way?

How about context switching, interrupts, and all the other unpredictable things?

In fact this whole topic is about the need to access data that exists in 8 byte chunks in global memory.  So much so that caches are a problem, causing congestion and wasted power. 

The 8031/8051 is a well known harvard architecture with separate I/D.

I'm most interested in Google's TPU, and thier work.  I'm working a brand new type of computer that operates using a different number system, one that doesn't use carry!  It's far more efficient at processing matrix operations that binary systems.  However, it doesn't address any of the issues of memory latentcy, and high speed I/O.  But darn, I sure would like to get 80 million in development funds, and the keep the patents too!

You can see some of the work at:  www.digitalsystemresearch.com

> Eric: I'm working a brand new type of computer that operates using a different number system, one that doesn't use carry!...I sure would like to get 80 million in development funds, and the keep the patents too!

All you have to do is search the BAAs and find one remotely related and send in your application. I don't know about $8 million, but $800,000 is entirely feasible.

Hi Colin,

Thanks for the advice.  Yes, I did notice the BAA's particularly in the area of new computing technology that your article is discussing.  It's very exciting, and I'm hoping that it allows more grass-roots original research to be funded.  We're a small company with no real recognition, so its highly unlikely that we would be funded by Darpa, but who know's, even in casino gaming a .01% chance might be worth the effort!  One thing is clear, without the backing of IC companies capable of advancing ideas with modern process technology, our idea doesn't have a chance.  Thank you for your article,  Eric