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You never caught me because I never did anything like that. You need to understa...
source link: https://twitter.com/andreif7/status/1350387890711363584
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there is no large time-of-flight! No oscilloscope needed.
So perhaps we even agree: you are saying on-package DRAM has "performance" benefits, which could mean lower power, lower BOM, fewer errors, slightly tighter timings, etc.
You are right there, but it has only a very small impact to software visible latency (what I meant by performance).
M1 gets its good memory performance large through improvements in the memory subsystem, not DRAM chip placement.
Part of François’s point (I believe) is that reducing memory interface power would allow you to spend more power on compute.
Then, the all world they don't understand ... Traces have impedance, impedance delays signal, here is the basic. https://ip.cadence.com/uploads/1012/Transmission_Line_WP_Final_0416-pdf…
Andrei calculous are a serious pile of blablabla for teenager or software guys trying to do hardware.
I never caught anything Andrei wrote regarding this stuff, and if you had asked me to solve the telegrapher's equations from memory I would start sweating pretty hard, but fortunately velocity factor tables do exist, and PCB stripline's value of ~45% is pretty easy to look up.
You never caught me because I never did anything like that. You need to understand that he lies on a routine basis, he didn't address the MLP claims, he didn't address the *measured* latency figures either even after this whole discussion. 
I hadn't more than skimmed your M1 article, but interpretive or editorial directions therein must have rather deeply disturbed Francois. 
I'll never know, since I've be (re)blocked, despite doing my best to be diplomatic here.
I was rather amused though when I got sent a link to another source he seems to think backs up his claims about PCB line delay magnitude, which was in fact yet another piece about line delay/length -discrepancies- (aka skew/timing budgets). PCB traces really aren't that slow.
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